Field of the Invention
The present invention relates to a method for altering a signal value for a field-programmable gate array (FPGA) at runtime. The invention also relates to a data processing device with a processor unit and an FPGA, wherein the data processing device is configured to perform the abovementioned method. The invention furthermore relates to a computer program product with computer-implemented prompts which upon charging and implementation in an appropriate data processing device is able to perform the steps of the abovementioned method. It also relates to a digital memory device with electronically readable control signals which can interact with a programmable data processing device in such a way that the abovementioned method can be performed. Lastly, the invention comprises a method for performing an FPGA build on the basis of an FPGA model in a hardware description language. The hardware description language can exist in text format, such as VHDL (VHSIC Hardware Description Language), or graphically, such as in the form of a Simulink Program.
Description of the Background Art
The real-time simulation of complex, dynamic models places high demands even on modern computation nodes due to the tight time constraints. In automotive hardware-in-the-loop simulations (HiL), such models are mainly used where there is a need to close fast control loops, e.g. for highly dynamic components of the environment model. This is the case, for example, with the simulation of cylinder pressure sensors which play an increasing role in the reduction of usage or emissions. However, also in controlled systems which exhibit high dynamics, such as for example in electric motors, short cycle times and low latencies are essential.
These can hardly be implemented any longer with CPU-based simulations. Also in the area of rapid control prototyping (RCP), more and more FPGAs are making their arrival as simulated environment models (e.g. simulated electric motor) or controlling devices must become more and more accurate and complex. In this context, for example, complex control parts are outsourced to an FPGA to ensure sufficiently precise and fast reaction times.
Field programmable gate arrays (FPGAs) are able to support computation nodes during real-time simulation by taking on the calculation of dynamic model parts. By using FPGAs, their high flexibility and option of parallel processing of signals can easily fulfill the difficult real-time demands. The FPGAs can serve as hardware accelerators for computation node CPUs. One example of such an extension of an HiL simulator is the DS5203-FPGA Board by dSPACE. Very dynamic parts of the environment model, e.g., are outsourced to the FPGA so that the controlling device is assured sufficiently precise and fast reaction times. An FPGA hardware configuration is typically generated based on an FPGA model in a hardware description language in a build process.
The models of a controlled system are becoming progressively complex due to increasing demands on precision and are thus difficult to manage. In the automotive HiL-environment, such models generally are created with the toolset Matlab/Simulink by The MathWorks, Inc. Simulink offers a block-based view of such models in the form of a block diagram. In a block diagram, model components can be combined into subsystems and linked to each other by signals. The flow of data between these blocks is in this case represented with signal lines.
In a CPU-based real-time simulation, the block diagram of a model is first converted to C/C++ source files with the help of the Simulink coder. The source files are then converted via a compiler into an executable application which can be run on a computation node with a real-time compatible operating system. Additionally, a trace file is generated at the CPU build which represents a topology file with its graphic modeling, e.g. in Simulink. A TRC file contains all accessible variables and displays the variables in memory locations. The variables can be stored in a topology similar to the one of the model.
The conversion of a model to a CPU-application has the result that the simulation calculations are performed sequentially in an incremental manner. A consistent image of all model conditions or model variables, e.g. data on the signal lines or input/output values of the blocks, is thereby always present in the main memory of the computation node. With direct access to the main memory, the model variables can be analyzed and/or manipulated in an experimental tool such as ControlDesk. An optional read-write access to variables of the HiL simulation is possible. Using the trace file, signal values such as engine speed can be selected and displayed or manipulated via a display. In the HiL-environment, this practice is typically summarized under the terms “measurement” and “adjustment”.
An FPGA-based simulation can be mapped in a block diagram with Simulink analog to the CPU-based simulation with the help of the Xilinx System Generator (XSG) and the FPGA Programming Blockset by dSPACE.
However, in contrast to the CPU-simulation, this model is not converted to an iterative programming language but instead to a hardware description language that writes to a customer-specific, digital circuit. The description of this customer-specific, digital circuit is converted to an FPGA configuration data stream via a synthesis process. Particularly in the realm of controlling device calibration for which a great number of parameters must be adjusted, a resource and time saving process is necessary. Calibration data is usually implemented as an invariable so that a change to the FPGA runtime is generally not possible.
For some FPGAs, it is possible to freeze and read out the complete state of the FPGA for debugging purposes. Due to the closed input/output data behavior of the FPGA, it is not possible to randomly access and possibly alter model states analog to the main memory of a computation node. Each model variable that the user wishes to measure or adjust must be guided to the FPGA interfaces through explicit modeling via signal lines. Following this adjustment, the model has to be newly converted which can take several hours. This factor can lead to very long development cycles of FPGA-based real-time simulations. Particularly in the realm of calibration, e.g. of controlling devices, this can call for a large number of resources if a great number of parameters need to be adjusted.